1. Field of the Invention
The present disclosure is generally related to a memory system protocol used for performing data operations (e.g., read, write) using memory devices. More specifically, the present disclosure is related to a packet-based scalable protocol that enables a number of memory and processing combinations, provides bit-efficient data transfer operations, and is concordant with a variety of bus types (e.g., electrical, optical).
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Conventional protocols generally transmit packets between memory devices with relatively low failure rates as compared with their predecessors. However, as industries aim to minimize the amount of energy involved in moving packets of data between memory devices and other components, it is desirable to use protocols that efficiently move packets of data using a minimal amount of energy, while maintaining the integrity of the packet transmission.